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? 2002 microchip technology inc. ds21298c-page 1 m mcp3204/3208 features ? 12-bit resolution ? 1 lsb max dnl ? 1 lsb max inl (mcp3204/3208-b) ? 2 lsb max inl (mcp3204/3208-c) ? 4 (mcp3204) or 8 (mcp3208) input channels ? analog inputs programmable as single-ended or pseudo-differential pairs ? on-chip sample and hold ? spi serial interface (modes 0,0 and 1,1) ? single supply operation: 2.7v - 5.5v ? 100 ksps max. sampling rate at v dd = 5v ? 50 ksps max. sampling rate at v dd = 2.7v ? low power cmos technology: - 500 na typical standby current, 2 a max. - 400 a max. active current at 5v ? industrial temp range: -40c to +85c ? available in pdip, soic and tssop packages applications ? sensor interface ? process control ? data acquisition ? battery operated systems package types description the microchip technology inc. mcp3204/3208 devices are successive approximation 12-bit analog- to-digital (a/d) converters with on-board sample and hold circuitry. the mcp3204 is programmable to pro- vide two pseudo-differential input pairs or four single- ended inputs. the mcp3208 is programmable to pro- vide four pseudo-differential input pairs or eight single- ended inputs. differential nonlinearity (dnl) is speci- fied at 1 lsb, while integral nonlinearity (inl) is offered in 1 lsb (mcp3204/3208-b) and 2 lsb (mcp3204/3208-c) versions. communication with the devices is accomplished using a simple serial interface compatible with the spi proto- col. the devices are capable of conversion rates of up to 100 ksps. the mcp3204/3208 devices operate over a broad voltage range (2.7v - 5.5v). low current design permits operation with typical standby and active currents of only 500 na and 320 a, respec- tively. the mcp3204 is offered in 14-pin pdip, 150 mil soic and tssop packages. the mcp3208 is offered in 16-pin pdip and soic packages. functional block diagram v dd clk d out mcp3204 1 2 3 4 14 13 12 11 10 9 8 5 6 7 v ref d in ch0 ch1 ch2 ch3 cs /shdn dgnd agnd nc v dd clk d out mcp3208 1 2 3 4 16 15 14 13 12 11 10 9 5 6 7 8 v ref d in cs /shdn dgnd ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 nc agnd pdip, soic, tssop pdip, soic comparator sample and hold 12-bit sar dac control logic cs /shdn v ref v ss v dd clk d out shift register ch0 channel mux input ch1 ch7* * note: channels 5-7 available on mcp3208 only d in 2.7v 4-channel/8-channel 12-bit a/d converters with spi ? serial interface
mcp3204/3208 ds21298c-page 2 ? 2002 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings* v dd ...................................................................................7.0v all inputs and outputs w.r.t. v ss ............... -0.6v to v dd +0.6v storage temperature .....................................-65c to +150c ambient temp. with power applied ................-65c to +125c soldering temperature of leads (10 seconds) ............. +300c esd protection on all pins.............................................> 4 kv * notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pin function table name function v dd +2.7v to 5.5v power supply dgnd digital ground agnd analog ground ch0-ch7 analog inputs clk serial clock d in serial data in d out serial data out cs /shdn chip select/shutdown input v ref reference voltage input electrical specifications electrical characteristics: unless otherwise noted, all parameters apply at v dd = 5v, v ss = 0v, v ref = 5v, t amb = -40c to +85c,f sample = 100 ksps and f clk = 20*f sample parameters sym min typ max units conditions conversion rate conversion time t conv ? ? 12 clock cycles analog input sample time t sample 1.5 clock cycles throughput rate f sample ? ? ? ? 100 50 ksps ksps v dd = v ref = 5v v dd = v ref = 2.7v dc accuracy resolution 12 bits integral nonlinearity inl ? ? 0.75 1.0 1 2 lsb mcp3204/3208-b mcp3204/3208-c differential nonlinearity dnl ? 0.5 1 lsb no missing codes over-temperature offset error ? 1.25 3 lsb gain error ? 1.25 5 lsb dynamic performance total harmonic distortion ? -82 ? db v in = 0.1v to 4.9v@1 khz signal to noise and distortion (sinad) ?72 ? dbv in = 0.1v to 4.9v@1 khz spurious free dynamic range ?86 ? dbv in = 0.1v to 4.9v@1 khz reference input voltage range 0.25 ? v dd v note 2 current drain ? ? 100 0.001 150 3.0 a a cs = v dd = 5v note 1: this parameter is established by characterization and not 100% tested. 2: see graphs that relate linearity performance to v ref levels. 3: because the sample cap will eventually lose charge, effective clock rates below 10 khz can affect linearity performance, particularly at elevated temperatures. see section 6.2, ?maintaining minimum clock speed?, for more information.
? 2002 microchip technology inc. ds21298c-page 3 mcp3204/3208 analog inputs input voltage range for ch0- ch7 in single-ended mode v ss ?v ref v input voltage range for in+ in pseudo-differential mode in- ? v ref +in- input voltage range for in- in pseudo-differential mode v ss -100 ? v ss +100 mv leakage current ? 0.001 1 a switch resistance ? 1000 ? ? see figure 4-1 sample capacitor ? 20 ? pf see figure 4-1 digital input/output data coding format straight binary high level input voltage v ih 0.7 v dd ??v low level input voltage v il ? ? 0.3 v dd v high level output voltage v oh 4.1 ? ? v i oh = -1 ma, v dd = 4.5v low level output voltage v ol ?? 0.4 vi ol = 1 ma, v dd = 4.5v input leakage current i li -10 ? 10 a v in = v ss or v dd output leakage current i lo -10 ? 10 a v out = v ss or v dd pin capacitance (all inputs/outputs) c in ,c out ? ? 10 pf v dd = 5.0v ( note 1 ) t amb = 25 c, f = 1 mhz timing parameters clock frequency f clk ? ? ? ? 2.0 1.0 mhz mhz v dd = 5v ( note 3 ) v dd = 2.7v ( note 3 ) clock high time t hi 250 ? ? ns clock low time t lo 250 ? ? ns cs fall to first rising clk edge t sucs 100 ? ? ns data input setup time t su ? ? 50 ns data input hold time t hd ? ? 50 ns clk fall to output data valid t do ? ? 200 ns see figures 1-2 and 1-3 clk fall to output enable t en ? ? 200 ns see figures 1-2 and 1-3 cs rise to output disable t dis ? ? 100 ns see figures 1-2 and 1-3 cs disable time t csh 500 ? ? ns d out rise time t r ? ? 100 ns see figures 1-2 and 1-3 ( note 1 ) d out fall time t f ? ? 100 ns see figures 1-2 and 1-3 ( note 1 ) power requirements operating voltage v dd 2.7 ? 5.5 v operating current i dd ? ? 320 225 400 ? a v dd =v ref = 5v, d out unloaded v dd =v ref = 2.7v, d out unloaded standby current i dds ?0.5 2.0 acs = v dd = 5.0v electrical specifications (continued) electrical characteristics: unless otherwise noted, all parameters apply at v dd = 5v, v ss = 0v, v ref = 5v, t amb = -40c to +85c,f sample = 100 ksps and f clk = 20*f sample parameters sym min typ max units conditions note 1: this parameter is established by characterization and not 100% tested. 2: see graphs that relate linearity performance to v ref levels. 3: because the sample cap will eventually lose charge, effective clock rates below 10 khz can affect linearity performance, particularly at elevated temperatures. see section 6.2, ?maintaining minimum clock speed?, for more information.
mcp3204/3208 ds21298c-page 4 ? 2002 microchip technology inc. figure 1-1: serial interface timing. temperature ranges specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +85 c storage temperature range t a -65 ? +150 c thermal package resistance thermal resistance, 14l-pdip ja ?70 ?c/w thermal resistance, 14l-soic ja ? 108 ? c/w thermal resistance, 14l-tssop ja ? 100 ? c/w thermal resistance, 16l-pdip ja ?70 ?c/w thermal resistance, 16l-soic ja ?90 ?c/w electrical specifications (continued) electrical characteristics: unless otherwise noted, all parameters apply at v dd = 5v, v ss = 0v, v ref = 5v, t amb = -40c to +85c,f sample = 100 ksps and f clk = 20*f sample parameters sym min typ max units conditions note 1: this parameter is established by characterization and not 100% tested. 2: see graphs that relate linearity performance to v ref levels. 3: because the sample cap will eventually lose charge, effective clock rates below 10 khz can affect linearity performance, particularly at elevated temperatures. see section 6.2, ?maintaining minimum clock speed?, for more information. cs clk d in msb in t su t hd t sucs t csh t hi t lo d out t en t do t r t f lsb msb out t dis null bit
? 2002 microchip technology inc. ds21298c-page 5 mcp3204/3208 figure 1-2: load circuit for t r , t f , t do . figure 1-3: load circuit for t dis and t en . te s t p o i n t 1.4v d out 3k ? c l = 100 pf d out t r voltage waveforms for t r , t f clk d out t do voltage waveforms for t do t f v oh v ol 90% 10% * waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. ? waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. tes t poi nt d out 3k ? 100 pf t dis waveform 2 t dis waveform 1 cs clk d out t en 12 b11 voltage waveforms for t en t en waveform v dd v dd /2 v ss 3 4 voltage waveforms for t dis d out d out cs v ih t dis waveform 1 * waveform 2 ?
mcp3204/3208 ds21298c-page 6 ? 2002 microchip technology inc. 2.0 typical performance characteristics note: unless otherwise indicated, v dd = v ref = 5v, v ss = 0v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-1: integral nonlinearity (inl) vs. sample rate. figure 2-2: integral nonlinearity (inl) vs. v ref . figure 2-3: integral nonlinearity (inl) vs. code (representative part). figure 2-4: integral nonlinearity (inl) vs. sample rate (v dd = 2.7v). figure 2-5: integral nonlinearity (inl) vs. v ref (v dd = 2.7v). figure 2-6: integral nonlinearity (inl) vs. code (representative part, v dd = 2.7v). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 255075100125150 sample rate (ksps) inl (lsb) positive inl negative inl -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 012345 vref (v) inl (lsb) positive inl negative inl -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 digital code inl (lsb) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 1020304050607080 sample rate (ksps) inl (lsb) positive inl negative inl v dd = v ref = 2.7 v -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 vref (v) inl (lsb) positive inl negative inl -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 digital code inl (lsb) v dd = v ref = 2.7 v f sample = 50 ksps
? 2002 microchip technology inc. ds21298c-page 7 mcp3204/3208 note: unless otherwise indicated, v dd = v ref = 5 v, v ss = 0 v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-7: integral nonlinearity (inl) vs. temperature. figure 2-8: differential nonlinearity (dnl) vs. sample rate. figure 2-9: differential nonlinearity (dnl) vs. v ref . figure 2-10: integral nonlinearity (inl) vs. temperature (v dd = 2.7v). figure 2-11: differential nonlinearity (dnl) vs. sample rate (v dd = 2.7v). figure 2-12: differential nonlinearity (dnl) vs. v ref (v dd = 2.7v) . -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 temperature (c) inl (lsb) positive inl negative inl -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 255075100125150 sample rate (ksps) dnl (lsb) positive dnl negative dnl -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 012345 vref (v) dnl (lsb) positive dnl negative dnl -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 temperature (c) inl (lsb) positive inl v dd = v ref = 2.7 v f sample = 50 ksps negative inl -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 1020304050607080 sample rate (ksps) dnl (lsb) positive dnl negative dnl v dd = v ref = 2.7 v -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 vref (v) dnl (lsb) v dd = v ref = 2.7 v f sample = 50 ksps positive dnl negative dnl
mcp3204/3208 ds21298c-page 8 ? 2002 microchip technology inc. note: unless otherwise indicated, v dd = v ref = 5v, v ss = 0v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-13: differential nonlinearity (dnl) vs. code (representative part). figure 2-14: differential nonlinearity (dnl) vs. temperature. figure 2-15: gain error vs. v ref . figure 2-16: differential nonlinearity (dnl) vs. code (representative part, v dd = 2.7v). figure 2-17: differential nonlinearity (dnl) vs. temperature (v dd = 2.7v). figure 2-18: offset error vs. v ref . -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 digital code dnl (lsb) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 temperature (c) dnl (lsb) positive dnl negative dnl -4 -3 -2 -1 0 1 2 3 4 012345 v ref (v) gain error (lsb) v dd = v ref = 2.7 v f sample = 50 ksps v dd = v ref = 5 v f sample = 100 ksps -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 digital code dnl (lsb) v dd = v ref = 2.7 v f sample = 50 ksps -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 temperature (c) dnl (lsb) positive dnl v dd = v ref = 2.7 v f sample = 50 ksps negative dnl 0 2 4 6 8 10 12 14 16 18 20 012345 v ref (v) offset error (lsb) v dd = v ref = 2.7v f sample = 50 ksps v dd = v ref = 5v f sample = 100 ksps
? 2002 microchip technology inc. ds21298c-page 9 mcp3204/3208 note: unless otherwise indicated, v dd = v ref = 5v, v ss = 0v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-19: gain error vs. temperature. figure 2-20: signal to noise (snr) vs. input frequency. figure 2-21: total harmonic distortion (thd) vs. input frequency. figure 2-22: offset error vs. temperature. figure 2-23: signal to noise and distortion (sinad) vs. input frequency. figure 2-24: signal to noise and distortion (sinad) vs. input signal level. -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 -50 -25 0 25 50 75 100 temperature (c) gain error (lsb) v dd = v ref = 5 v f sample = 100 ksps v dd = v ref = 2.7 v f sample = 50 ksps 0 10 20 30 40 50 60 70 80 90 100 110100 input frequency (khz) snr (db) v dd = v ref = 2.7v f sample = 50 ksps v dd = v ref = 5 v f sample = 100 ksps -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 110100 input frequency (khz) thd (db) v dd = v ref = 5v f sample = 100 ksps v dd = v ref = 2.7v f sample = 50 ksps 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50-250 255075100 temperature (c) offset error (lsb) v dd = v ref = 5 v f sample = 100 ksps v dd = v ref = 2.7 v f sample = 50 ksps 0 10 20 30 40 50 60 70 80 90 100 110100 input frequency (khz) sfdr (db) v dd = v ref = 5 v f sample = 100 ksps v dd = v ref = 2.7 v f sample = 50 ksps 0 10 20 30 40 50 60 70 80 -40 -35 -30 -25 -20 -15 -10 -5 0 input signal level (db) sinad (db) v dd = v ref = 2.7 v f sample = 50 ksps v dd = v ref = 5 v f sample = 100 ksps
mcp3204/3208 ds21298c-page 10 ? 2002 microchip technology inc. note: unless otherwise indicated, v dd = v ref = 5v, v ss = 0v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-25: effective number of bits (enob) vs. v ref . figure 2-26: spurious free dynamic range (sfdr) vs. input frequency. figure 2-27: frequency spectrum of 10 khz input (representative part). figure 2-28: effective number of bits (enob) vs. input frequency. figure 2-29: power supply rejection (psr) vs. ripple frequency. figure 2-30: frequency spectrum of 1 khz input (representative part, v dd = 2.7v). 9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75 11.00 11.25 11.50 11.75 12.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v ref (v) enob (rms) v dd = v ref = 2.7 v f sample = 50 ksps v dd = v ref = 5 v f sample =100 ksps 0 10 20 30 40 50 60 70 80 90 100 110100 input frequency (khz) sfdr (db) v dd = v ref = 5 v f sample = 100 ksps v dd = v ref = 2.7 v f sample = 50 ksps -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 10000 20000 30000 40000 50000 frequency (hz) amplitude (db) v dd = v ref = 5 v f sample = 100 ksps f input = 9.985 khz 4096 points 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 110100 input frequency (khz) enob (rms) v dd = v ref = 2.7 v f sample = 50 ksps v dd = v ref = 5 v f sample = 100 ksps -80 -70 -60 -50 -40 -30 -20 -10 0 1 10 100 1000 10000 ripple frequency (khz) power supply rejection (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 5000 10000 15000 20000 25000 frequency (hz) amplitude (db) v dd = v ref = 2.7 v f sample = 50 ksps f input = 998.76 hz 4096 points
? 2002 microchip technology inc. ds21298c-page 11 mcp3204/3208 note: unless otherwise indicated, v dd = v ref = 5v, v ss = 0v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-31: i dd vs. v dd . figure 2-32: i dd vs. clock frequency. figure 2-33: i dd vs. temperature. figure 2-34: i ref vs. v dd . figure 2-35: i ref vs. clock frequency. figure 2-36: i ref vs. temperature. 0 50 100 150 200 250 300 350 400 450 500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) i dd (a) v ref = v dd all points at f clk = 2 mhz, except at v ref = v dd = 2.5 v, f clk = 1 mhz 0 50 100 150 200 250 300 350 400 10 100 1000 10000 clock frequency (khz) i dd (a) v dd = v ref = 5 v v dd = v ref = 2.7 v 0 50 100 150 200 250 300 350 400 -50-250 255075100 temperature (c) i dd (a) v dd = v ref = 5 v f clk = 2 mhz v dd = v ref = 2.7 v f clk = 1 mhz 0 10 20 30 40 50 60 70 80 90 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) i ref (a) v ref = v dd all points at f clk = 2 mhz except at v ref = v dd = 2.5 v, f clk = 1 mhz 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 clock frequency (khz) i ref (a) v dd = v ref = 5 v v dd = v ref = 2.7 v 0 10 20 30 40 50 60 70 80 90 100 -50-250 255075100 temperature (c) i ref (a) v dd = v ref = 5 v f clk = 2 mhz v dd = v ref = 2.7 v f clk = 1 mhz
mcp3204/3208 ds21298c-page 12 ? 2002 microchip technology inc. note: unless otherwise indicated, v dd = v ref = 5v, v ss = 0v, f sample = 100 ksps, f clk = 20* f sample ,t a = 25c. figure 2-37: i dds vs. v dd . figure 2-38: i dds vs. temperature. figure 2-39: analog input leakage current vs. temperature. 0 10 20 30 40 50 60 70 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) i dds (pa) v ref = cs = v dd 0.01 0.10 1.00 10.00 100.00 -50 -25 0 25 50 75 100 temperature (c) i dds (na) v dd = v ref = cs = 5 v 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 temperature (c) analog input leakage (na) v dd = v ref = 5 v f clk = 2 mhz
? 2002 microchip technology inc. ds21298c-page 13 mcp3204/3208 3.0 pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 dgnd digital ground connection to internal digital circuitry. 3.2 agnd analog ground connection to internal analog circuitry. 3.3 ch0 - ch7 analog inputs for channels 0 - 7 for the multiplexed inputs. each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input, where one channel is in+ and one channel is in. see section 4.1, ?analog inputs?, and section 5.0, ?serial communications?, for information on programming the channel configuration. 3.4 serial clock (clk) the spi clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. see section 6.2, ?maintaining minimum clock speed?, for constraints on clock speed. 3.5 serial data input (d in ) the spi port serial data input pin is used to load channel configuration data into the device. 3.6 serial data output (d out ) the spi serial data output pin is used to shift out the results of the a/d conversion. data will always change on the falling edge of each clock as the conversion takes place. 3.7 chip select /shutdown (cs /shdn) the cs /shdn pin is used to initiate communication with the device when pulled low and will end a conver- sion and put the device in low power standby when pulled high. the cs /shdn pin must be pulled high between conversions. 4.0 device operation the mcp3204/3208 a/d converters employ a conven- tional sar architecture. with this architecture, a sam- ple is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the serial clock after the start bit has been received. fol- lowing this sample time, the device uses the collected charge on the internal sample/hold capacitor to pro- duce a serial 12-bit digital output code. conversion rates of 100 ksps are possible on the mcp3204/3208. see section 6.2, ?maintaining minimum clock speed?, for information on minimum clock rates. communica- tion with the device is accomplished using a 4-wire spi- compatible interface. 4.1 analog inputs the mcp3204/3208 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. the mcp3204 can be configured to provide two pseudo-differential input pairs or four single-ended inputs, while the mcp3208 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. configuration is done as part of the serial command before each con- version begins. when used in the pseudo-differential mode, each channel pair (i.e., ch0 and ch1, ch2 and ch3 etc.) is programmed to be the in+ and in- inputs as part of the command string transmitted to the device. the in+ input can range from in- to (v ref + in- ). the in- input is limited to 100 mv from the v ss rail. the in- input can be used to cancel small signal com- mon-mode noise which is present on both the in+ and in- inputs. when operating in the pseudo-differential mode, if the voltage level of in+ is equal to or less than in-, the resultant code will be 000h . if the voltage at in+ is equal to or greater than {[v ref + (in-)] - 1 lsb}, then the output code will be fffh . if the voltage level at in- is more than 1 lsb below v ss , the voltage level at the in+ input will have to go below v ss to see the 000h output code. conversely, if in- is more than 1 lsb above v ss , then the fffh code will not be seen unless the in+ input level goes above v ref level. for the a/d converter to meet specification, the charge holding capacitor (c sample ) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. the analog input model is shown in figure 4-1. name function v dd +2.7v to 5.5v power supply dgnd digital ground agnd analog ground ch0-ch7 analog inputs clk serial clock d in serial data in d out serial data out cs /shdn chip select/shutdown input v ref reference voltage input
mcp3204/3208 ds21298c-page 14 ? 2002 microchip technology inc. this diagram illustrates that the source impedance (r s ) adds to the internal sampling switch (r ss ) impedance, directly effecting the time that is required to charge the capacitor (csample). consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see figure 4-2). 4.2 reference input for each device in the family, the reference input (v ref ) determines the analog input voltage range. as the reference input is reduced, the lsb size is reduced accordingly. the theoretical digital output code pro- duced by the a/d converter is a function of the analog input signal and the reference input, as shown below. equation when using an external voltage reference device, the system designer should always refer to the manufac- turer?s recommendations for circuit layout. any instabil- ity in the operation of the reference device will have a direct effect on the operation of the a/d converter. figure 4-1: analog input model. figure 4-2: maximum clock frequency vs. input resistance (r s ) to maintain less than a 0.1 lsb deviation in inl from nominal conditions. digital output code 4096 v in v ref -------------------------- - = v in = analog input voltage v ref = reference voltage c pin va r ss chx 7pf v t = 0.6v v t = 0.6v i leakage sampling switch ss r s = 1 k ? c sample = dac capacitance v ss v dd = 20 pf 1 na legend va = signal source i leakage = leakage current at the pin due to various junctions r ss = source impedance ss = sampling switch chx = input channel pad r s = sampling switch resistor c pin = input pin capacitance c sample = sample/hold capacitance v t = threshold voltage 0.0 0.5 1.0 1.5 2.0 2.5 100 1000 10000 input resistance (ohms) clock frequency (mhz) v dd = 5 v v dd = 2.7 v
? 2002 microchip technology inc. ds21298c-page 15 mcp3204/3208 5.0 serial communications communication with the mcp3204/3208 devices is accomplished using a standard spi-compatible serial interface. initiating communication with either device is done by bringing the cs line low (see figure 5-1). if the device was powered up with the cs pin low, it must be brought high and back low to initiate communication. the first clock received with cs low and d in high will constitute a start bit. the sgl/diff bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. the next three bits (d0, d1 and d2) are used to select the input channel configuration. table 5-1 and table 5-2 show the configuration bits for the mcp3204 and mcp3208, respectively. the device will begin to sample the ana- log input on the fourth rising edge of the clock after the start bit has been received. the sample period will end on the falling edge of the fifth clock following the start bit. once the d0 bit is input, one more clock is required to complete the sample and hold period (d in is a ?don?t care? for this clock). on the falling edge of the next clock, the device will output a low null bit. the next 12 clocks will output the result of the conversion with msb first, as shown in figure 5-1. data is always output from the device on the falling edge of the clock. if all 12 data bits have been transmitted and the device continues to receive clocks while the cs is held low, the device will output the conversion result lsb first, as shown in figure 5-2. if more clocks are provided to the device while cs is still low (after the lsb first data has been transmitted), the device will clock out zeros indefinitely. if necessary, it is possible to bring cs low and clock in leading zeros on the d in line before the start bit. this is often done when dealing with microcontroller-based spi ports that must send 8 bits at a time. refer to section 6.1 for more details on using the mcp3204/ 3208 devices with hardware spi ports. table 5-1: configuration bits for the mcp3204 table 5-2: configuration bits for the mcp3208 control bit selections input configuration channel selection single/ diff d2* d1 d0 1 x 0 0 single-ended ch0 1 x 0 1 single-ended ch1 1 x 1 0 single-ended ch2 1 x 1 1 single-ended ch3 0 x 0 0 differential ch0 = in+ ch1 = in- 0 x 0 1 differential ch0 = in- ch1 = in+ 0 x 1 0 differential ch2 = in+ ch3 = in- 0 x 1 1 differential ch2 = in- ch3 = in+ * d2 is a ?don?t care? for mcp3204 control bit selections input configuration channel selection single /diff d2 d1 d0 1 0 0 0 single-ended ch0 1 0 0 1 single-ended ch1 1 0 1 0 single-ended ch2 1 0 1 1 single-ended ch3 1 1 0 0 single-ended ch4 1 1 0 1 single-ended ch5 1 1 1 0 single-ended ch6 1 1 1 1 single-ended ch7 0 0 0 0 differential ch0 = in+ ch1 = in- 0 0 0 1 differential ch0 = in- ch1 = in+ 0 0 1 0 differential ch2 = in+ ch3 = in- 0 0 1 1 differential ch2 = in- ch3 = in+ 0 1 0 0 differential ch4 = in+ ch5 = in- 0 1 0 1 differential ch4 = in- ch5 = in+ 0 1 1 0 differential ch6 = in+ ch7 = in- 0 1 1 1 differential ch6 = in- ch7 = in+
mcp3204/3208 ds21298c-page 16 ? 2002 microchip technology inc. figure 5-1: communication with the mcp3204 or mcp3208. figure 5-2: communication with mcp3204 or mcp3208 in lsb first format. cs clk d in d out d1 d2 d0 hi-z don?t care null bit b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 * hi-z t sample t conv sgl/ diff start t cyc t csh t cyc d2 sgl/ diff start * after completing the data transfer, if further clocks are applied with cs low, the a/d converter will output lsb first data, followed by zeros indefinitely (see figure 5-2 below). ** t data : during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the clk running to clock out the lsb-first data or zeros. t data ** t sucs null bit b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10b11 cs clk d out hi-z hi-z (msb) t conv t data ** power down t sample start sgl/ diff d in t cyc t csh d0 d1 d2 * after completing the data transfer, if further clocks are applied with cs low, the a/d converter will output zeros indefinitely. ** t data : during this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the clk running to clock out lsb first data or zeroes. t sucs don?t care *
? 2002 microchip technology inc. ds21298c-page 17 mcp3204/3208 6.0 applications information 6.1 using the mcp3204/3208 with microcontroller (mcu) spi ports with most microcontroller spi ports, it is required to send groups of eight bits. it is also required that the microcontroller spi port be configured to clock out data on the falling edge of clock and latch data in on the ris- ing edge. because communication with the mcp3204/ 3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. this is usually done by sending ?leading zeros? before the start bit. as an example, figure 6-1 and figure 6-2 illustrate how the mcp3204/3208 can be interfaced to a mcu with a hardware spi port. figure 6-1 depicts the operation shown in spi mode 0,0, which requires that the sclk from the mcu idles in the ?low? state, while figure 6-2 shows the similar case of spi mode 1,1, where the clock idles in the ?high? state. as is shown in figure 6-1, the first byte transmitted to the a/d converter contains five leading zeros before the start bit. arranging the leading zeros this way allows the output 12 bits to fall in positions easily manipulated by the mcu. the msb is clocked out of the a/d converter on the falling edge of clock number 12. once the second eight clocks have been sent to the device, the mcu?s receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conversion. once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. employing this method ensures simpler manipulation of the converted data. figure 6-2 shows the same thing in spi mode 1,1, which requires that the clock idles in the high state. as with mode 0,0, the a/d converter outputs data on the falling edge of the clock and the mcu latches data from the a/d converter in on the rising edge of the clock.
mcp3204/3208 ds21298c-page 18 ? 2002 microchip technology inc. figure 6-1: spi communication using 8-bit segments (mode 0,0: sclk idles low). figure 6-2: spi communication using 8-bit segments (mode 1,1: sclk idles high). 1234 5678 9101112131415 16 cs sclk d in x = ?don?t care? bits 17 18 19 20 21 22 23 24 d out null bit b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 hi-z mcu latches data from a/d data is clocked out of a/d converter on falling edges converter on rising edges of sclk do don?t care sgl/ diff d1 d2 start 00000 1 xx xxx do xxxxxxxx b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 0 ???????? ??? d1 d2 sgl/ diff start bit (null) mcu transmitted data (aligned with falling edge of clock) mcu received data (aligned with rising edge of clock) x data stored into mcu receive register after transmission of first 8 bits data stored into mcu receive register after transmission of second 8 bits data stored into mcu receive register after transmission of last 8 bits don?t care 000001 xx xxx do xxxxxxxx b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 0 ???????? ??? d1 d2 sgl/ diff (null) x 23 b1 x 1234 567 8 9101112131415 16 cs sclk d in x = ?don?t care? bits 17 18 19 20 21 22 23 24 d out do don?t care null bit b11 b10 b9 b8 b6 b5 b4 b3 b2 b1 b0 hi-z 000001 xxxxx do sgl/ diff xxxxxxxx b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 0 ???????? ??? mcu latches data from a/d converter on rising edges of sclk data is clocked out of a/d converter on falling edges d1 d2 sgl/ diff start bit (null) d1 d2 start mcu transmitted data (aligned with fa lling edge of clock) mcu received data (aligned with rising edge of clock) b7 x data stored into mcu receive register after transmission of first 8 bits data stored into mcu receive register after transmission of second 8 bits data stored into mcu receive register after transmission of last 8 bits do
? 2002 microchip technology inc. ds21298c-page 19 mcp3204/3208 6.2 maintaining minimum clock speed when the mcp3204/3208 initiates the sample period, charge is stored on the sample capacitor. when the sample period is complete, the device converts one bit for each clock that is received. it is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. at 85c (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. this means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 khz). failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. it should be noted that during the entire conversion cycle, the a/d converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. 6.3 buffering/filtering the analog inputs if the signal source for the a/d converter is not a low impedance source, it will have to be buffered or inaccu- rate conversion results may occur (see figure 4-2). it is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results, as is illustrated in figure 6-3, where an op amp is used to drive the analog input of the mcp3204/3208. this amplifier provides a low impedance source for the converter input, and a low pass filter, which eliminates unwanted high frequency noise. low pass (anti-aliasing) filters can be designed using microchip?s free interactive filterlab? software. filter- lab w ill calculate c apacitor and resistor values, as well as determine the number of poles that are required for the application. for more information on filtering sig- nals, see an699, ?anti-aliasing analog filters for data acquisition systems? . figure 6-3: the mcp601 operational amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the mcp3204. mcp3204 v dd 10 f in- in+ - + v in c 1 c 2 v ref 4.096v reference 1f 1f 0.1 f mcp601 r 1 r 2 r 3 r 4 mcp1541
mcp3204/3208 ds21298c-page 20 ? 2002 microchip technology inc. 6.4 layout considerations when laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. a bypass capacitor should always be used with this device, placed as close as possible to the device pin. a bypass capacitor value of 1 f is recommended. digital and analog traces should be separated as much as possible on the board, with no traces running under- neath the device or the bypass capacitor. extra precau- tions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. providing v dd connections to devices in a ?star? configuration can also reduce noise by eliminating return current paths and associated errors (see figure 6-4). for more information on layout tips when using a/d converters, refer to an688, ?layout tips for 12-bit a/d converter applications? . figure 6-4: v dd traces arranged in a ?star? configuration in order to reduce errors caused by current return paths. 6.5 utilizing the digital and analog ground pins the mcp3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. as shown in figure 6-5, the analog and digital circuitry is separated internal to the device. this reduces noise from the digital portion of the device being coupled into the analog portion of the device. the two grounds are connected internally through the sub- strate, which has a resistance of 5 -10 ? . if no ground plane is utilized, then both grounds must be connected to v ss on the board. if a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. if both an analog and a digital ground plane are available, both the digital and the analog ground pins should be con- nected to the analog ground plane. following these steps will reduce the amount of digital noise from the rest of the board being coupled into the a/d converter. figure 6-5: separation of analog and digital ground pins. v dd connection device 1 device 2 device 3 device 4 mcp3204/08 analog ground plane dgnd agnd v dd 0.1 f substrate 5 - 10 ? digital side -spi interface -shift register -control logic analog side -sample cap -capacitor array -comparator
? 2002 microchip technology inc. ds21298c-page 21 mcp3204/3208 7.0 packaging information 7.1 package marking information legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). for marking beyond this, certain price adders apply. please check with your microchip sales office. 14-lead pdip (300 mil) example: 14-lead soic (150 mil) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxx yywwnnn mcp3204 -b i/p yywwnnn xxxxxxxxxxx mcp3204 -b yywwnnn xxxxxxxxxxx xxxxxxxx nnn yyww 14-lead tssop (4.4mm) * example: 3204 -c nnn iyww * please contact microchip factory for b-grade tssop devices
mcp3204/3208 ds21298c-page 22 ? 2002 microchip technology inc. package marking information (continued) 16-lead pdip (300 mil) ( mcp3304 )example: 16-lead soic (150 mil) ( mcp3304 ) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxxxxx yywwnnn mcp3208 -b i/p yywwnnn xxxxxxxxxxxxx mcp3208 -b iywwnnn xxxxxxxxxx
? 2002 microchip technology inc. ds21298c-page 23 mcp3204/3208 14-lead plastic dual in-line (p) ? 300 mil (pdip) e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
mcp3204/3208 ds21298c-page 24 ? 2002 microchip technology inc. 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic
? 2002 microchip technology inc. ds21298c-page 25 mcp3204/3208 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b1 lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
mcp3204/3208 ds21298c-page 26 ? 2002 microchip technology inc. 16-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 .036 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 19.30 19.05 18.80 .760 .750 .740 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 16 16 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-017 significant characteristic
? 2002 microchip technology inc. ds21298c-page 27 mcp3204/3208 16-lead plastic small outline (sl) ? narrow 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 10.01 9.91 9.80 .394 .390 .386 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.44 1.32 .061 .057 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 16 16 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 e1 1 2 l h n b 45 e p d c a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-108 significant characteristic
mcp3204/3208 ds21298c-page 28 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21298c-page29 mcp3204/3208 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development systems, technical information and more ? listing of seminars and events 092002
mcp3204/3208 ds21298c-page30 ? 2002 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21298c mcp3204/3208
? 2002 microchip technology inc. ds21298c-page31 mcp3204/08 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. device: mcp3204: 4-channel 12-bit serial a/d converter mcp3204t: 4-channel 12-bit serial a/d converter (tape and reel) mcp3208: 8-channel 12-bit serial a/d converter mcp3208t: 8-channel 12-bit serial a/d converter (tape and reel) grade: b = 1 lsb inl c=2lsb inl temperature range: i = -40c to +85c package: p = plastic dip (300 mil body), 14-lead, 16-lead sl = plastic soic (150 mil body), 14-lead, 16-lead st = plastic tssop (4.4mm), 14-lead examples: a) mcp3204-bi/p: 1 lsb inl, industrial tem- perature, pdip package. b) mcp3204-bi/sl: 1 lsb inl, industrial temperature, soic package. c) mcp3204-ci/st: 2 lsb inl, industrial temperature, tssop package. a) mcp3208-bi/p: 1 lsb inl, industrial temperature, pdip package. b) mcp3208-bi/sl: 1 lsb inl, industrial temperature, soic package. c) mcp3208-ci/st: 2 lsb inl, industrial temperature, tssop package. part no. x /xx package temperature range device x grade
mcp3204/08 ds21298c-page 32 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21298c - page 33 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, k ee l oq , mplab, pic, picmicro, picstart and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. dspic, dspicdem.net, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds21298c-page 34 ? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 china - hong kong sar microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 ta iw a n microchip technology (barbados) inc., taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria microchip technology austria gmbh durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom microchip ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 08/01/02 w orldwide s ales and s ervice

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